Silicon carbide semiconductor device

ABSTRACT

A gate insulating film is provided on a trench. The gate insulating film has a trench insulating film and a bottom insulating film. The trench insulating film covers each of a side wall and a bottom portion. The bottom insulating film is provided on the bottom portion with a trench insulating film being interposed therebetween. The bottom insulating film has a carbon atom concentration lower than that of the trench insulating film. The gate electrode is in contact with a portion of the trench insulating film on the side wall. Accordingly, a low threshold voltage and a large breakdown voltage can be attained.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a silicon carbide semiconductor device,in particular, a silicon carbide semiconductor device having a trench.

2. Description of the Background Art

Japanese Patent Laying-Open No. 7-326755 discloses a trench gate typeMOSFET (Metal Oxide Semiconductor Field Effect Transistor) employing asilicon carbide substrate. This patent publication describes that a gatethermal oxidation film has a thicker film thickness on a bottom surfaceof a trench than the film thickness thereof on a side surface of thetrench, so that a threshold voltage becomes low and breakdown voltagebetween the gate and the drain becomes high. It is also described thatthe bottom surface of the trench corresponds to a carbon plane, whichallows for fast oxidation rate, of hexagonal single-crystal siliconcarbide, whereas the side surface of the trench corresponds to a planeperpendicular to this carbon plane and allowing for slow oxidation rate.Hence, by performing a thermal oxidation process once, a thermaloxidation film can be formed such that the thickness of the thermaloxidation film on the side surface of the trench is greatly differentfrom the thickness of the thermal oxidation film on the bottom surfaceof the trench.

According to the technique of the above-described patent publication,the gate insulating film on the trench is entirely formed by the thermaloxidation on the trench of the silicon carbide substrate. The siliconcarbide substrate used here normally has a high crystallinity, so that athin and flat gate insulating film can be formed. In this way, lowthreshold voltage can be attained. However, in the insulating film thusformed by the thermal oxidation of silicon carbide, carbon atoms, whichhave existed in the silicon carbide, remains to an extent that cannot bedisregarded. According to a study conducted by the present inventors,the carbon atoms remaining in the gate oxide film decrease dielectricbreakdown resistance of the gate insulating film. Accordingly, it isconsidered that there is room for further improvement for the dielectricbreakdown resistance in the above-described conventional technique.Namely, it is considered that there is room for further increasing thebreakdown voltage of the silicon carbide semiconductor device.

SUMMARY OF THE INVENTION

The present invention has been made to solve the foregoing problem andhas its object to provide a silicon carbide semiconductor device havinga low threshold voltage and a large breakdown voltage.

A silicon carbide semiconductor device of the present inventionincludes: a silicon carbide substrate, a gate insulating film, and agate electrode. The silicon carbide substrate includes first to thirdlayers. The first layer has first conductivity type. The second layer isprovided on the first layer and has second conductivity type. The thirdlayer is provided on the second layer, is separated from the first layerby the second layer, and has the first conductivity type. The siliconcarbide substrate is provided with a trench. The trench includes a sidewall and a bottom portion, the side wall extending through the thirdlayer and the second layer and reaching the first layer, the bottomportion being formed of the first layer. The gate insulating film isprovided on the trench. The gate insulating film includes a trenchinsulating film and a bottom insulating film. The trench insulating filmcovers each of the side wall and the bottom portion. The bottominsulating film is provided on the bottom portion with the trenchinsulating film being interposed therebetween. The bottom insulatingfilm has a carbon atom concentration lower than that of the trenchinsulating film. The gate electrode is provided in the trench. The gateelectrode is in contact with a portion of the trench insulating film onthe side wall.

According to this silicon carbide semiconductor device, electricinsulation between the gate electrode and the bottom portion of thetrench is secured by the bottom insulating film in addition to thetrench insulating film. With the low carbon atom concentration, thebottom insulating film has a high dielectric breakdown resistance.Accordingly, the silicon carbide semiconductor device has a largebreakdown voltage. Further, according to the silicon carbidesemiconductor device, the gate electrode is in contact with the portionof the trench insulating film on the side wall. Namely, the gateelectrode faces the side wall that forms a channel, without the bottominsulating film being interposed therebetween. Thus, the bottominsulating film is disposed so as not to increase the threshold voltage.Accordingly, a low threshold voltage is attained without influence ofthe bottom insulating film.

Preferably, a total of a thickness of the trench insulating film on thebottom portion and a thickness of the bottom insulating film is largerthan a thickness of the trench insulating film on the side wall.Accordingly, the thickness of the gate insulating film can be made smallon the side wall whereas the thickness thereof can be made large on thebottom portion. Accordingly, the breakdown voltage of the siliconcarbide semiconductor device can be made larger while making thethreshold voltage small.

Preferably, on the bottom portion, a thickness of the bottom insulatingfilm is larger than that of the trench insulating film. Accordingly, aratio of the portion formed of the bottom insulating film of the gateinsulating film is made large on the bottom portion. This leads to alarger breakdown voltage of the silicon carbide semiconductor device.

Preferably, a thickness of the trench insulating film on the bottomportion is smaller than a thickness of the trench insulating film on theside wall. Accordingly, a region for providing the bottom insulatingfilm is further secured on the bottom portion. This leads to a largerbreakdown voltage of the silicon carbide semiconductor device.

Preferably, the carbon atom concentration of the trench insulating filmis more than 1×10¹⁵ cm⁻³, and the carbon atom concentration of thebottom insulating film is less than 1×10¹⁵ cm⁻³. Accordingly, the carbonatom concentration in the bottom insulating film is sufficiently madelow. This leads to a larger breakdown voltage of the silicon carbidesemiconductor device.

Preferably, the bottom insulating film has a thickness of more than 100nm. This leads to a larger breakdown voltage of the silicon carbidesemiconductor device.

Preferably, the trench insulating film is a thermal oxidation film ofsilicon carbide. This makes the trench insulating film thin and smooth.This leads to a larger breakdown voltage of the silicon carbidesemiconductor device.

Preferably, the bottom insulating film is formed of at least any one ofsilicon oxide, silicon nitride, and phosphorus silicate glass. Thisleads to a larger breakdown voltage of the silicon carbide semiconductordevice.

Preferably, the bottom insulating film is a thermal oxidation film of afilm containing silicon and containing no carbon. This leads to a largerbreakdown voltage of the silicon carbide semiconductor device.

As described above, according to the present invention, a low thresholdvoltage and a large breakdown voltage are attained.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a partial cross sectional view schematically showing aconfiguration of a silicon carbide semiconductor device in a firstembodiment of the present invention.

FIG. 2 is a perspective view schematically showing a shape of a siliconcarbide substrate included in the silicon carbide semiconductor deviceof FIG. 1.

FIG. 3 shows the configuration of FIG. 2 more in detail with a region ofsecond conductivity type being provided with hatching for viewability ofthe figure.

FIG. 4 is an enlarged view of FIG. 1.

FIG. 5 is a graph showing a profile of a carbon atom concentration alongan arrow Z in FIG. 4.

FIG. 6 is a partial cross sectional view schematically showing a firststep of a method for manufacturing the silicon carbide semiconductordevice of FIG. 1.

FIG. 7 is a partial cross sectional view schematically showing a secondstep of the method for manufacturing the silicon carbide semiconductordevice of FIG. 1.

FIG. 8 is a partial cross sectional view schematically showing a thirdstep of the method for manufacturing the silicon carbide semiconductordevice of FIG. 1.

FIG. 9 is a partial cross sectional view schematically showing a fourthstep of the method for manufacturing the silicon carbide semiconductordevice of FIG. 1.

FIG. 10 is a partial cross sectional view schematically showing a fifthstep of the method for manufacturing the silicon carbide semiconductordevice of FIG. 1.

FIG. 11 is a partial cross sectional view schematically showing a sixthstep of the method for manufacturing the silicon carbide semiconductordevice of FIG. 1.

FIG. 12 is a partial cross sectional view schematically showing aseventh step of the method for manufacturing the silicon carbidesemiconductor device of FIG. 1.

FIG. 13 is a partial cross sectional view schematically showing aneighth step of the method for manufacturing the silicon carbidesemiconductor device of FIG. 1.

FIG. 14 is a partial cross sectional view schematically showing a ninthstep of the method for manufacturing the silicon carbide semiconductordevice of FIG. 1.

FIG. 15 is a partial cross sectional view schematically showing a tenthstep of the method for manufacturing the silicon carbide semiconductordevice of FIG. 1.

FIG. 16 is a partial cross sectional view schematically showing aneleventh step of the method for manufacturing the silicon carbidesemiconductor device of FIG. 1.

FIG. 17 is a partial cross sectional view schematically showing atwelfth step of the method for manufacturing the silicon carbidesemiconductor device of FIG. 1.

FIG. 18 is a partial cross sectional view schematically showing athirteenth step of the method for manufacturing the silicon carbidesemiconductor device of FIG. 1.

FIG. 19 is a partial cross sectional view schematically showing one stepof a method for manufacturing a silicon carbide semiconductor device ofa comparative example.

FIG. 20 is a partial cross sectional view schematically showing aconfiguration of a silicon carbide semiconductor device in a secondembodiment of the present invention.

FIG. 21 is a partial cross sectional view schematically showing a finestructure in a surface of a silicon carbide substrate included in thesilicon carbide semiconductor device.

FIG. 22 shows a crystal structure of a (000-1) plane in a hexagonalcrystal of polytype 4H.

FIG. 23 shows a crystal structure of a (11-20) plane along a lineXXIII-XXIII in FIG. 22.

FIG. 24 shows a crystal structure of a combined plane of FIG. 21 in thevicinity of the surface within the (11-20) plane.

FIG. 25 shows the combined plane of FIG. 21 when viewed from a (01-10)plane.

FIG. 26 is a graph showing an exemplary relation between channelmobility and an angle between a channel surface and the (000-1) planewhen macroscopically viewed, in each of a case where thermal etching isperformed and a case where no thermal etching is performed.

FIG. 27 is a graph showing an exemplary relation between the channelmobility and an angle between a channel direction and a <0-11-2>direction.

FIG. 28 shows a modification of FIG. 21.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following describes embodiments of the present invention based onfigures. It should be noted that in the below-mentioned figures, thesame or corresponding portions are given the same reference charactersand are not described repeatedly. Regarding crystallographic indicationsin the present specification, an individual orientation is representedby [ ], a group orientation is represented by < >, and an individualplane is represented by ( ) and a group plane is represented by { }. Inaddition, a negative crystallographic index is normally expressed byputting “-” (bar) above a numeral, but is expressed by putting thenegative sign before the numeral in the present specification.

First Embodiment

As shown in FIG. 1, a vertical type MOSFET 500 (silicon carbidesemiconductor device) of the present embodiment includes an epitaxialsubstrate 100 (silicon carbide substrate), gate insulating films 201,gate electrodes 202, interlayer insulating films 203, source electrodes221, a drain electrode 211, a source interconnection 222, and aprotecting electrode 212.

Epitaxial substrate 100 is made of silicon carbide, and has asingle-crystal substrate 110 and an epitaxial layer provided thereon.The epitaxial layer includes an n⁻layer 121 (first layer), p type bodylayers 122 (second layer), n regions 123 (third layer), and contactregions 124. The silicon carbide of epitaxial substrate 100 preferablyhas a hexagonal crystal structure, more preferably, has a polytype of4H.

Single-crystal substrate 110 has n type (first conductivity type)conductivity. The plane orientation (hklm) of one main surface (uppersurface in FIG. 1) of single-crystal substrate 110 preferably has m ofnegative value, more preferably, corresponds to approximately a (000-1)plane.

N⁻layer 121 has a donor added therein and therefore has n typeconductivity. The donor is preferably added to n⁻layer 121 by adding animpurity during epitaxial growth of n⁻layer 121, rather than ionimplantation. N⁻layer 121 preferably has a donor concentration lowerthan that of single-crystal substrate 110. N⁻layer 121 preferably has adonor concentration of not less than 1×10¹⁵ cm⁻³ and not more than5×10¹⁶ cm⁻³, for example, has a donor concentration of 8×10¹⁵ cm⁻³.

Each of p type body layers 122 is provided on n⁻layer 121, has anacceptor added therein, and therefore has p type conductivity (secondconductivity type). P type body layer 122 has an acceptor concentrationof, for example, 1×10¹⁸ cm⁻³.

Each of n regions 123 has n type conductivity. N region 123 is providedon p type body layer 122, and is separated from n layer 121 by p typebody layer 122. Contact region 124 has p type conductivity. Contactregion 124 is formed on a portion of p type body layer 122 so as to beconnected to p type body layer 122.

Further, referring to FIG. 2 and FIG. 3, epitaxial substrate 100 isprovided with a trench TR. Trench TR has side walls SW and a bottomportion BT. Each of side walls SW extends through n region 123 and ptype body layer 122 and reaches n layer 121. Bottom portion BT is formedof n layer 121. Side wall SW has a channel surface CH on p type bodylayer 122 (FIG. 3). Bottom portion BT is a flat surface substantiallyparallel to the main surface of epitaxial substrate 100. Preferably,side wall SW has a predetermined crystal plane (also referred to as“special plane”) particularly on p type body layer 122. Details of thespecial plane will be described later.

The fact that epitaxial substrate 100 has trench TR corresponds to sucha fact that the epitaxial layer is partially removed above the uppersurface of single-crystal substrate 110. In the present embodiment, amultiplicity of mesa structures are formed on the upper surface ofsingle-crystal substrate 110. Specifically, each of the mesa structureshas upper surface and bottom portion both having a hexagonal shape, andhas side walls inclined relative to the main surface of single-crystalsubstrate 110. Thus, trench TR expands toward the opening in a taperingmanner.

Gate insulating film 201 is provided on trench TR. Gate insulating film201 separates epitaxial substrate 100 and gate electrode 202 from eachother in trench TR. Gate insulating film 201 has a trench insulatingfilm 201A and a bottom insulating film 201B. Trench insulating film 201Acovers each of side walls SW and bottom portion BT. Bottom insulatingfilm 201B is provided on bottom portion BT with trench insulating film201A being interposed therebetween. Bottom insulating film 201B has aportion located at a corner portion formed by bottom portion BT and eachside wall SW.

Bottom insulating film 201B has a carbon atom concentration lower thanthat of trench insulating film 201A. Preferably, trench insulating film201A is a thermal oxidation film of silicon carbide. In this case,trench insulating film 201A is made of silicon oxide containing carbonatoms as an impurity. Preferably, bottom insulating film 201B is athermal oxidation film of a film containing silicon and containing nocarbon. In the present embodiment, bottom insulating film 201B is athermal oxidation film of a silicon film, and is made of silicon oxide.

As shown in FIG. 4, trench insulating film 201A has a thickness t1 onside wall SW and has a thickness t2 on bottom portion BT. Bottominsulating film 201B has a thickness t3 on bottom portion BT.Preferably, a total of thickness t2 and thickness t3 is larger thanthickness t1. Preferably, thickness t3 is larger than thickness t2.Preferably, thickness t2 is smaller than thickness t1. Preferably,thickness t3 is larger than 100 nm.

Trench insulating film 201A may have a carbon atom concentration of morethan 1×10¹⁵ cm⁻³. Bottom insulating film 201B preferably has a carbonatom concentration of less than 1×10¹⁵ cm⁻³. It should be noted that inthe case where the carbon atom concentrations are not uniform, anaverage value may be calculated.

Further, referring to FIG. 5, a solid line of FIG. 5 illustrates aprofile of a carbon atom concentration NC in the thickness direction(arrow Z in FIG. 4) from the bottom portion BT toward the trench. Alocation Z=0 corresponds to an interface between bottom portion BT andtrench insulating film 201A. A location Z=t2 corresponds to an interfacebetween trench insulating film 201A and bottom insulating film 201B. Alocation Z=t2+t3 corresponds to an interface between bottom insulatingfilm 201B and gate electrode 202. When 0≦z≦t2, carbon atom concentrationNC becomes smaller as Z increases. In the vicinity of Z=0 (arrow d1 inthe figure), the decrease of carbon atom concentration NC is relativelygradual. When Z>t2, carbon atom concentration NC substantially reachesor falls below the detection limit. In the vicinity of location Z=0,trench insulating film 201A typically has a carbon atom concentration NCof more than approximately 1×10¹⁷ cm⁻³ and less than approximately1×10²⁰ cm⁻³, for example, has a carbon atom concentration NC ofapproximately 1×10¹⁸ cm⁻³.

Gate electrode 202 is provided in trench TR. Specifically, gateelectrode 202 is buried in trench TR with gate insulating film 201interposed therebetween. Gate electrode 202 is in contact with trenchinsulating film 201A at a portion located on side wall SW. On side wallSW, gate electrode 202 faces the surface of p type body layer 122 withonly trench insulating film 201A being interposed therebetween. In otherwords, bottom insulating film 201B is not provided between the portionof trench insulating film 201A on side wall SW and gate electrode 202.Gate electrode 202 has an upper surface substantially as high as theupper surface of a portion of gate insulating film 201 on the uppersurface of n region 123. Interlayer insulating film 203 is provided tocover gate electrode 202 as well as the extended portion of gateinsulating film 201 on the upper surface of n region 123.

Source electrode 221 extends through interlayer insulating film 203 andmakes contact with each of n regions 123 and contact region 124. Sourceinterconnection 222 is provided on source electrode 221 and interlayerinsulating film 203 in contact with source electrode 221. Drainelectrode 211 is provided on an opposite surface of epitaxial substrate100 to its surface in which trench TR is provided. Protecting electrode212 covers drain electrode 211.

The following describes a method for manufacturing MOSFET 500 (FIG. 1).

As shown in FIG. 6, on single-crystal substrate 110, n⁻layer 121 isformed by means of epitaxial growth. This epitaxial growth can beperformed by means of, for example, a CVD (Chemical Vapor Deposition)method in which a mixed gas of silane (SiH₄) and propane (C₃H₈) is usedas a source material gas and hydrogen gas (H₂) is used as a carrier gas,for example. In doing so, it is preferable to introduce nitrogen (N) orphosphorus (P) as a donor, for example.

As shown in FIG. 7, p type body layer 122 is formed on n′ layer 121, andn region 123 is formed on p type body layer 122. Specifically, ionimplantation is performed into the upper surface of n⁻layer 121. In theion implantation for forming p type body layer 122, ions of an acceptorsuch as aluminum (Al) are implanted. Meanwhile, in the ion implantationfor forming n region 123, ions of a donor such as phosphorus (P) areimplanted, for example. Accordingly, epitaxial substrate 100 is formedwhich has n⁻layer 121, p type body layer 122, and n region 123. Itshould be noted that instead of the ion implantation, epitaxial growthinvolving addition of impurities may be employed.

As shown in FIG. 8, by means of the ion implantation, contact regions124 are formed. Next, activation heating treatment is performed toactivate the impurities added by the ion implantation. This heattreatment is preferably performed at a temperature of not less than1500° C. and not more than 1900° C., for example, a temperature ofapproximately 1700° C. The heat treatment is performed for approximately30 minutes, for example. The atmosphere of the heat treatment ispreferably an inert gas atmosphere, such as Ar atmosphere.

Next, a mask 247 (FIG. 9) having an opening through which n region 123is partially exposed is formed on epitaxial substrate 100. The openingis formed to correspond to the location of trench TR (FIG. 1). As mask247, a silicon oxide film formed through thermal oxidation can be used,for example.

As shown in FIG. 10, in the opening of mask 247, n region 123, p typebody layer 122, and a portion of n⁻layer 121 are removed by etching. Anexemplary, usable etching method is reactive ion etching (RIB), inparticular, inductively coupled plasma (ICP) RIE. Specifically, ICP-RIEcan be employed in which SF₆ or a mixed gas of SF₆ and O₂ is used as thereactive gas, for example. By means of such etching, in the region wheretrench TR (FIG. 1) is to be formed, a recess TQ can be formed which hasa side wall having an inner surface SV substantially perpendicular tothe main surface of single-crystal substrate 110.

Next, using mask 247, epitaxial substrate 100 is etched. Specifically,inner surface SV of recess TQ of epitaxial substrate 100 is thermallyetched. The thermal etching can be performed by, for example, heatingepitaxial substrate 100 in an atmosphere including a reactive gascontaining at least one or more types of halogen atom. The at least oneor more types of halogen atom include at least one of chlorine (Cl) atomand fluorine (F) atom. This atmosphere is, for example, Cl₂, BCL₃, SF₆,or CF₄. For example, the thermal etching is performed using a mixed gasof chlorine gas and oxygen gas as a reactive gas, at a heat treatmenttemperature of, for example, not less than 700° C. and not more than1000° C.

As a result of the thermal etching, trench TR is formed as shown in FIG.11. During the formation of trench TR, epitaxial substrate 100 is etchedin a side etching manner from the opening of mask 247 as indicated by anarrow SE. Further, during this thermal etching, a special plane isspontaneously formed in side wall SW of trench TR, in particular, itsportion formed of p type body layer 122.

It should be noted that the reactive gas may contain a carrier gas inaddition to the chlorine gas and the oxygen gas. An exemplary, usablecarrier gas is nitrogen (N₂) gas, argon gas, helium gas, or the like.When the heat treatment temperature is set at not less than 700° C. andnot more than 1000° C. as described above, a rate of etching SiC isapproximately, for example, 70 μm/hour. In addition, in this case, mask247, which is formed of silicon oxide and therefore has a very largeselection ratio relative to SiC, is not substantially etched during theetching of SiC.

As shown in FIG. 12, a silicon film 90 is formed on epitaxial substrate100 having mask 247 provided thereon. In other words, silicon film 90 isformed while using mask 247. Silicon film 90 is formed on bottom portionBT of trench TR. This formation can be performed by means of, forexample, the CVD method. Next, mask 247 is removed by means of anappropriate method such as etching (FIG. 13). In doing so, the portionof silicon film 90 on mask 247 is also removed.

Next, oxidation is performed in trench TR, thereby forming gateinsulating film 201 (FIG. 1) on trench TR. Specifically, the followingsteps are performed. First, silicon film 90 (FIG. 13) is thermallyoxidized. Accordingly, an silicon oxide film is formed (FIG. 14) whichserves as bottom insulating film 201B that forms a portion of gateinsulating film 201 (FIG. 1). Silicon film 90 is thermally oxidized at,for example, not less than 800° C. and not more than 950° C. Next, asshown in FIG. 15, epitaxial substrate 100 made of silicon carbide isthermally oxidized, thereby forming an silicon oxide film serving astrench insulating film 201A of gate insulating film 201. Epitaxialsubstrate 100 is preferably thermally oxidized at a temperature higherthan the temperature at which silicon film 90 is thermally oxidized, forexample, is thermally oxidized at 1300° C. or more.

As shown in FIG. 16, gate electrode 202 is formed on gate insulatingfilm 201. Gate electrode 202 is formed in direct contact with trenchinsulating film 201A on p type body layer 122. A method for forming gateelectrode 202 can be performed by, for example, forming a film ofconductor or doped polysilicon and performing CMP (Chemical MechanicalPolishing).

As shown in FIG. 17, interlayer insulating film 203 is formed on gateelectrode 202 and gate insulating film 201 so as to cover the exposedsurface of gate electrode 202. Referring to FIG. 18, etching isperformed to form openings in interlayer insulating film 203 and gateinsulating film 201. Through the opening, each of n region 123 andcontact region 124 is exposed on the upper surface of the mesastructure. Next, on the upper surface of the mesa structure, sourceelectrode 221 is formed in contact with each of n region 123 and contactregion 124. Referring to FIG. 1 again, source interconnection 222, drainelectrode 211, and protecting electrode 212 are formed. In this way,MOSFET 500 is obtained.

According to MOSFET 500 (FIG. 4) of the present embodiment, electricinsulation between gate electrode 202 and bottom portion BT of trench TRis secured by bottom insulating film 201B in addition to trenchinsulating film 201A. Bottom insulating film 201B has a low carbon atomconcentration, and therefore has a high dielectric breakdown resistance.Accordingly, MOSFET 500 has a large breakdown voltage. Further,according to this MOSFET 500, gate electrode 202 is in contact with theportion of trench insulating film 201A on side wall SW. Namely, gateelectrode 202 faces side wall SW that forms a channel, without bottominsulating film 201B being interposed therebetween. Thus, bottominsulating film 201B is disposed so as not to increase the thresholdvoltage. Accordingly, a low threshold voltage is attained withoutinfluence of bottom insulating film 201B.

Further, trench insulating film 201A is a thermal oxidation film ofsilicon carbide of epitaxial substrate 100 (see FIG. 14 and FIG. 15).This makes the trench insulating film thin and smooth. Accordingly, thebreakdown voltage of MOSFET 500 can be made larger.

Further, bottom insulating film 201B is made of silicon oxide. In thisway, the breakdown voltage of MOSFET 500 can be made larger. Further,bottom insulating film 201B is silicon film 90, i.e., a thermaloxidation film of a film containing silicon and containing no carbon. Inthis way, the breakdown voltage of MOSFET 500 can be made larger.

When t2+t3>t1, the thickness of gate insulating film 201 can be madesmall on side wall SW whereas the thickness thereof can be made large onbottom portion BT. Accordingly, the breakdown voltage of MOSFET 500 canbe made larger while making the threshold voltage small.

When t3>t2, a ratio of the portion formed of bottom insulating film 201Bof gate insulating film 201 becomes large on bottom portion BT.Accordingly, the breakdown voltage of MOSFET 500 can be made larger.

When t2<t1, a region for providing bottom insulating film 201B isfurther secured on bottom portion BT. Accordingly, the breakdown voltageof MOSFET 500 can be made larger.

When t3>100 nm, the breakdown voltage of MOSFET 500 can be made larger.

When bottom insulating film 201B has a carbon atom concentration of lessthan 1×10¹⁵ cm⁻³, the carbon atom concentration of bottom insulatingfilm 201B is sufficiently low. Accordingly, the breakdown voltage ofMOSFET 500 can be made larger.

Further, according to the present embodiment, the decrease of carbonatom concentration NC in gate insulating film 201 just above bottomportion BT of trench TR (FIG. 5) is relatively gradual as indicated byarrow d1 (FIG. 5). Accordingly, generation of stress due to thecomposition change in gate insulating film 201 can be suppressed. Incontrast, if a gate insulating film 201Z is formed by means of thermaloxidation of epitaxial substrate 100 without bottom insulating film 201B(FIG. 15) as shown in FIG. 19, carbon atom concentration NC isdrastically decreased in gate insulating film 201Z just above bottomportion BT of trench TR as indicated by arrow d2 (FIG. 5). As a result,stress is likely to be applied to gate insulating film 201Z.

It should be noted that in the present embodiment, the silicon oxidefilm serving as bottom insulating film 201B (FIG. 14) is a silicon oxidefilm formed through the thermal oxidation of silicon film 90 (FIG. 13),but the silicon oxide film may be formed through, for example, the CVDmethod instead of forming silicon film 90. Further, the material of thebottom insulating film is not limited to silicon oxide, and may bephosphorus silicate glass or silicon nitride, for example. A film madeof silicon nitride can be formed by means of, for example, the CVDmethod.

Further, the “first conductivity type” corresponds to n typeconductivity, and the “second conductivity type” corresponds to p typeconductivity, but these conductivity types may be replaced with eachother. In this case, the donor and acceptor in the foregoing descriptionare also replaced with each other. It should be noted that in order toattain higher channel mobility, it is preferable that the “firstconductivity type” corresponds to n type conductivity. Further, thesilicon carbide semiconductor device is not limited to the MOSFET, andmay be a trench type IGBT (Insulated Gate Bipolar Transistor), forexample.

Second Embodiment

As shown in FIG. 20, a MOSFET 500 v (silicon carbide semiconductordevice) of the present embodiment has a trench TRv having a V shapeinstead of trench TR (FIG. 4). Trench TRv has a bottom portion BTv,instead of bottom portion BT (FIG. 4). When viewed in cross section(FIG. 20), bottom portion BTv is a portion in which side walls SW facingeach other make contact with each other so as to form a V shape. Apartfrom the configuration described above, the configuration of the presentembodiment is substantially the same as the configuration of the firstembodiment. Hence, the same or corresponding elements are given the samereference characters and are not described repeatedly.

(Surface Having Special Plane)

As described above, side wall SW (FIG. 1) of trench TR preferably has apredetermined crystal plane (also referred to as “special plane”) on, inparticular, p type body layer 122. Such a side wall SW includes a planeS1 (first plane) having a plane orientation of {0-33-8} as shown in FIG.21. Plane S1 preferably has a plane orientation of (0-33-8).

More preferably, side wall SW microscopically includes plane S1, andside wall SW microscopically further includes a plane S2 (second plane)having a plane orientation of {0-11-1}. Here, the term “microscopically”refers to “minutely to such an extent that at least the size about twiceas large as an interatomic spacing is considered”. As a method forobserving such a microscopic structure, for example, a TEM (TransmissionElectron Microscope) can be used. Preferably, plane S2 has a planeorientation of (0-11-1).

Preferably, plane S1 and plane S2 of side wall SW forms a combined planeSR having a plane orientation of {0-11-2}. Specifically, combined planeSR is formed of periodically repeated planes S1 and S2. Such a periodicstructure can be observed by, for example, TEM or AFM (Atomic ForceMicroscopy). In this case, combined plane SR has an off angle of 62°relative to the {000-1} plane, macroscopically. Here, the term“macroscopically” refers to “disregarding a fine structure having a sizeof approximately interatomic spacing”. For the measurement of such amacroscopic off angle, a method employing general X-ray diffraction canbe used, for example. Preferably, combined plane SR has a planeorientation of (0-11-2). In this case, combined plane SR has an offangle of 62° relative to the (000-1) plane, macroscopically.

Preferably, in the channel surface, carriers flow in a channel directionCD, in which the above-described periodic repetition is done.

The following describes detailed structure of combined plane SR.

Generally, regarding Si atoms (or C atoms), when viewing a siliconcarbide single-crystal of polytype 4H from the (000-1) plane, atoms in alayer A (solid line in the figure), atoms in a layer B (broken line inthe figure) disposed therebelow, and atoms in a layer C (chain line inthe figure) disposed therebelow, and atoms in a layer B (not shown inthe figure) disposed therebelow are repeatedly provided as shown in FIG.22. In other words, with four layers ABCB being regarded as one period,a periodic stacking structure such as ABCBABCBABCB . . . is provided.

As shown in FIG. 23, in the (11-20) plane (cross section taken along aline XXIII-XXIII of FIG. 22), atoms in each of four layers ABCBconstituting the above-described one period are not aligned completelyalong the (0-11-2) plane. In FIG. 23, the (0-11-2) plane is illustratedto pass through the locations of the atoms in layers B. In this case, itis understood that each of atoms in layers A and C is deviated from the(0-11-2) plane. Hence, even when the macroscopic plane orientation ofthe surface of the silicon carbide single-crystal, i.e., the planeorientation thereof with its atomic level structure being ignored islimited to (0-11-2), this surface can have various structuresmicroscopically.

As shown in FIG. 24, combined plane SR is constructed by alternatelyproviding planes S1 having a plane orientation of (0-33-8) and planes S2connected to planes S1 and having a plane orientation different fromthat of each of planes S1. Each of planes S1 and S2 has a length twiceas large as the interatomic spacing of the Si atoms (or C atoms). Itshould be noted that a plane with plane S1 and plane S2 being averagedcorresponds to the (0-11-2) plane (FIG. 23).

As shown in FIG. 25, when viewing combined plane SR from the (01-10)plane, the single-crystal structure has a portion periodically includinga structure (plane S1 portion) equivalent to a cubic structure.Specifically, combined plane SR is constructed by alternately providingplanes S1 having a plane orientation of (001) in the above-describedstructure equivalent to the cubic structure and planes S2 connected toplanes S1 and having a plane orientation different from that of each ofplanes S1. Also in a polytype other than 4H, the surface can be formedof the planes (planes S1 in FIG. 25) having a plane orientation of (001)in the structure equivalent to the cubic structure and the planes(planes S2 in FIG. 25) connected to the foregoing planes and having aplane orientation different from that of each of the foregoing planes.The polytype may be, for example, 6H or 15R.

Referring to FIG. 26, the following describes a relation between thecrystal plane of side wall SW and mobility MB of the channel surface. Inthe graph of FIG. 26, the horizontal axis represents an angle D1 formedby the (000-1) plane and the macroscopic plane orientation of side wallSW having the channel surface, whereas the vertical axis representsmobility MB. A group of plots CM correspond to a case where side wall SWis finished to correspond to a special plane by thermal etching, whereasa group of plots MC correspond to a case where side wall SW is notthermally etched.

In group of plots MC, mobility MB is at maximum when the surface of thechannel surface has a macroscopic plane orientation of (0-33-8). This ispresumably due to the following reason. That is, in the case where thethermal etching is not performed, i.e., in the case where themicroscopic structure of the channel surface is not particularlycontrolled, the macroscopic plane orientation thereof corresponds to(0-33-8), with the result that a ratio of the microscopic planeorientation of (0-33-8), i.e., the plane orientation of (0-33-8) inconsideration of that in atomic level becomes statistically high.

On the other hand, mobility MB in group of plots CM is at maximum whenthe macroscopic plane orientation of the channel surface is (0-11-2)(arrow EX). This is presumably due to the following reason. That is, asshown in FIG. 24 and FIG. 25, the multiplicity of planes S1 each havinga plane orientation of (0-33-8) are densely and regularly arranged withplanes S2 interposed therebetween, whereby a ratio of the microscopicplane orientation of (0-33-8) becomes high in the surface of the channelsurface.

It should be noted that mobility MB has orientation dependency oncombined plane SR. In a graph shown in FIG. 27, the horizontal axisrepresents an angle D2 between the channel direction and the <0-11-2>direction, whereas the vertical axis represents mobility MB (in anyunit) in the channel surface. A broken line is supplementarily providedtherein for viewability of the graph. From this graph, it has been foundthat in order to increase channel mobility MB, channel direction CD(FIG. 21) preferably has an angle D2 of not less than 0° and not morethan 60°, more preferably, substantially 0°.

As shown in FIG. 28, side wall SW may further include plane S3 (thirdplane) in addition to combined plane SR. More specifically, side wall SWmay include a combined plane SQ formed of periodically repeated plane S3and combined plane SR. In this case, the off angle of side wall SWrelative to the {000-1} plane is deviated from the ideal off angle ofcombined plane SR, i.e., 62°. Preferably, this deviation is small,preferably, in a range of ±10°. Examples of a surface included in suchan angle range include a surface having a macroscopic plane orientationof the {0-33-8} plane. More preferably, the off angle of side wall SWrelative to the (000-1) plane is deviated from the ideal off angle ofcombined plane SR, i.e., 62°. Preferably, this deviation is small,preferably, in a range of ±10°. Examples of a surface included in suchan angle range include a surface having a macroscopic plane orientationof the (0-33-8) plane.

Such a periodic structure can be observed by, for example, TEM or AFM.Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the scopeof the present invention being interpreted by the terms of the appendedclaims.

What is claimed is:
 1. A silicon carbide semiconductor devicecomprising: a silicon carbide substrate including a first layer havingfirst conductivity type, a second layer provided on said first layer andhaving second conductivity type, and a third layer provided on saidsecond layer, separated from said first layer by said second layer, andhaving said first conductivity type, said silicon carbide substratebeing provided with a trench having a side wall and a bottom portion,said side wall extending through said third layer and said second layerand reaching said first layer, said bottom portion being formed of saidfirst layer; a gate insulating film provided on said trench, said gateinsulating film including a trench insulating film and a bottominsulating film, said trench insulating film covering each of said sidewall and said bottom portion, said bottom insulating film being providedon said bottom portion with said trench insulating film being interposedtherebetween, said bottom insulating film having a carbon atomconcentration lower than that of said trench insulating film; and a gateelectrode provided in said trench, said gate electrode being in contactwith a portion of said trench insulating film on said side wall.
 2. Thesilicon carbide semiconductor device according to claim 1, wherein atotal of a thickness of said trench insulating film on said bottomportion and a thickness of said bottom insulating film is larger than athickness of said trench insulating film on said side wall.
 3. Thesilicon carbide semiconductor device according to claim 1, wherein onsaid bottom portion, a thickness of said bottom insulating film islarger than that of said trench insulating film.
 4. The silicon carbidesemiconductor device according to claim 1, wherein a thickness of saidtrench insulating film on said bottom portion is smaller than athickness of said trench insulating film on said side wall.
 5. Thesilicon carbide semiconductor device according to claim 1, wherein thecarbon atom concentration of said trench insulating film is more than1×10¹⁵ cm⁻³, and the carbon atom concentration of said bottom insulatingfilm is less than 1×10¹⁵ cm⁻³.
 6. The silicon carbide semiconductordevice according to claim 1, wherein said bottom insulating film has athickness of more than 100 nm.
 7. The silicon carbide semiconductordevice according to claim 1, wherein said trench insulating film is athermal oxidation film of silicon carbide.
 8. The silicon carbidesemiconductor device according to claim 1, wherein said bottominsulating film is formed of at least any one of silicon oxide, siliconnitride, and phosphorus silicate glass.
 9. The silicon carbidesemiconductor device according to claim 1, wherein said bottominsulating film is a thermal oxidation film of a film containing siliconand containing no carbon.